The Derivation of Energy-Efficient Pipelines

We discuss the design of energy-efficient pipelines for asynchronous VLSI architectures. To maximize throughput in asyn-chronous pipelines it is often necessary to insert buffer stages, increasing the energy overhead. Instead of optimizing pipelines for minimum energy or maximum throughput, we consider a joint energy-time metric of the form ¼ is the energy per operation and ½ is the time per operation. We show that pipelines optimized for the ¼  ½  ¾ energy-time metric may need fewer buffer stages and we give bounds when such stages can be removed. We present several common asynchronous pipeline structures and their energy-time optimized solutions.